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?2012 fairchild semiconductor corporation fdb3632_f085 rev. c1 fdb3632_f085 fdb3632_f085 n-channel powertrench ? mosfet 100v, 80a, 9m ? features r ds(on) = 7.5m ? (typ.), v gs = 10v, i d = 80a q g (tot) = 84nc (typ.), v gs = 10v low miller charge low q rr body diode uis capability (single pulse and repetitive pulse) qualified to aec q101 applications dc/dc converters and off-line ups distributed power architectures and vrms primary switch for 24v and 48v systems high voltage synchronous rectifier direct injection / diesel injection systems 42v automotive load control electronic valve train systems mosfet maximum ratings t c = 25c unless otherwise noted thermal characteristics this product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. for a copy of the requirements, see aec q101 at: http://www.aec ounc il.com/ reliability data can be found at: http://www.fairchildsemi.com/pr oducts/discrete/reliability/index.html. all fairchild semiconductor products are manufactured, assembled and tested under iso 9000 and qs9000 quality systems certification. symbol parameter ratings units v dss drain to source voltage 100 v v gs gate to source voltage 20 v i d drain current 80 a continuous (t c < 111 o c, v gs = 10v) continuous (t amb = 25 o c, v gs = 10v, r ja = 43 o c/w) 12 a pulsed figure 4 a e as single pulse avalanche energy (note 1) 338 mj p d power dissipation 310 w derate above 25 o c2.07w/ o c t j , t stg operating and storage temperature -55 to +175 o c r jc thermal resistance junction to case to-220, to-263, to-262 0.48 o c/w r ja thermal resistance junction to ambient to-220, to-262 (note 2) 62 o c/w r ja thermal resistance junction to ambient to-263, 1in 2 copper pad area 43 o c/w s g d to-263ab fdb series gate source drain (flange) march 2012 rohs compliant
package marking and ordering information electrical characteristics t c = 25c unless otherwise noted off characteristics on characteristics dynamic characteristics resistive switching characteristics (v gs = 10v) drain-source diode characteristics notes: 1: starting t j = 25c, l = 0.12mh, i as = 75a. 2: pulse width = 100s device marking device package reel size tape width quantity fdb3632 fdb3632_f085 to-263ab 330mm 24mm 800 units symbol parameter test conditions min typ max units b vdss drain to source breakdown voltage i d = 250 a, v gs = 0v 100 - - v i dss zero gate voltage drain current v ds = 80v - - 1 a v gs = 0v t c = 150 o c- - 250 i gss gate to source leakage current v gs = 20v - - 100 na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a2-4v r ds(on) drain to source on resistance i d =80a, v gs =10v - 0.0075 0.009 ? i d =80a, v gs =10v, t c =175 o c - 0.018 0.022 c iss input capacitance v ds = 25v, v gs = 0v, f = 1mhz -6000- pf c oss output capacitance - 820 - pf c rss reverse transfer capacitance - 200 - pf q g(tot) total gate charge at 10v v gs = 0v to 10v v dd = 50v i d = 80a i g = 1.0ma -84110nc q g(th) threshold gate charge v gs = 0v to 2v - 11 14 nc q gs gate to source gate charge - 30 - nc q gs2 gate charge threshold to plateau - 20 - nc q gd gate to drain ?miller? charge - 20 - nc t on tur n -o n t im e v dd = 50v, i d = 80a v gs = 10v, r gs = 3.6 ? --102ns t d(on) tur n -o n d e lay ti me - 30 - ns t r rise time - 39 - ns t d(off) turn-off delay time - 96 - ns t f fall time - 46 - ns t off turn-off time - - 213 ns v sd source to drain diode voltage i sd = 80a - - 1.25 v i sd = 40a - - 1.0 v t rr reverse recovery time i sd = 75a, di sd /dt= 100a/ s- - 64 ns q rr reverse recovered charge i sd = 75a, di sd /dt= 100a/ s - - 120 nc ?2012 fairchild semiconductor corporation fdb3632_f085 rev. c1 fdb3632_f085
fdb3632_f085 ?2012 fairchild semiconductor corporation fdb3632_f085 rev. c1 typical characteristics t a = 25c unless otherwise noted figure 1. normalized power dissipation vs ambient temperature figure 2. maximum continuous drain current vs case temperature figure 3. normalized maximu m transient thermal impedance figure 4. peak current capability t c , case temperature ( o c) power dissipation multiplier 0 0255075100 175 0.2 0.4 0.6 0.8 1.0 1.2 125 150 0 25 50 75 100 125 25 50 75 100 125 150 175 i d , drain current (a) t c , case temperature ( o c) v gs = 10v current limited by package 0.01 0.1 1 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 2 t, rectangular pulse duration (s) z jc , normalized thermal impedance notes: duty factor: d = t 1 /t 2 peak t j = p dm x z jc x r jc + t c p dm t 1 t 2 0.5 0.2 0.1 0.05 0.01 0.02 duty cycle - descending order single pulse 100 1000 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 50 2000 i dm , peak current (a) t, pulse width (s) transconductance may limit current in this region v gs = 10v t c = 25 o c i = i 25 175 - t c 150 for temperatures above 25 o c derate peak current as follows:
fdb3632_f085 ?2012 fairchild semiconductor corporation fdb3632_f085 rev. c1 figure 5. forward bias safe operating area note: refer to fairchild application notes an7514 and an7515 figure 6. unclamped inductive switching capability figure 7. transfer characteristics f igure 8. saturation characteristics figure 9. drain to sour ce on resistance vs drain current figure 10. normalized drain to source on resistance vs junction temperature typical characteristics t a = 25c unless otherwise noted 0.1 1 10 100 110100 200 400 i d , drain current (a) v ds , drain to source voltage (v) t j = max rated t c = 25 o c single pulse limited by r ds(on) area may be operation in this 10 s 10ms 1ms dc 100 s 10 100 0.1 1 10 200 0.01 i as , avalanche current (a) t av , time in avalanche (ms) starting t j = 25 o c starting t j = 150 o c t av = (l)(i as )/(1.3*rated bv dss - v dd ) if r = 0 if r 0 t av = (l/r)ln[(i as *r)/(1.3*rated bv dss - v dd ) +1] 0 30 60 90 120 150 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i d , drain current (a) v gs , gate to source voltage (v) pulse duration = 80 s duty cycle = 0.5% max v dd = 15v t j = 175 o c t j = 25 o c t j = -55 o c 0 30 60 90 120 150 01234 i d , drain current (a) v ds , drain to source voltage (v) v gs = 5.5v pulse duration = 80 s duty cycle = 0.5% max v gs = 5v t c = 25 o c v gs = 10v v gs = 6v 6 7 8 9 10 0 2 04 06 28 0 i d , drain current (a) v gs = 10v drain to source on resistance (m ? ) v gs = 6v pulse duration = 80 s duty cycle = 0.5% max 0.5 1.0 1.5 2.0 2.5 -80 -40 0 40 80 120 160 200 normalized drain to source t j , junction temperature ( o c) on resistance v gs = 10v, i d =80a pulse duration = 80 s duty cycle = 0.5% max
fdb3632_f085 ?2012 fairchild semiconductor corporation fdb3632_f085 rev. c1 figure 11. normalized gate threshold voltage vs junction temperature figure 12. normalized drain to source breakdown voltage vs junction temperature figure 13. capacita nce vs drain to source voltage figure 14. gate charge waveforms for constant gate currents typical characteristics t a = 25c unless otherwise noted 0.2 0.4 0.6 0.8 1.0 1.2 1.4 -80 -40 0 40 80 120 160 200 normalized gate t j , junction temperature ( o c) v gs = v ds , i d = 250 a threshold voltage 0.9 1.0 1.1 1.2 -80 -40 0 40 80 120 160 200 t j , junction temperature ( o c) normalized drain to source i d = 250 a breakdown voltage 100 1000 10000 0.1 1 10 100 c, capacitance (pf) v gs = 0v, f = 1mhz c iss = c gs + c gd c oss ? c ds + c gd c rss = c gd v ds , drain to source voltage (v) 0 2 4 6 8 10 0 20406080100 v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 50v i d = 80a i d = 40a waveforms in descending order:
fdb3632_f085 ?2012 fairchild semiconductor corporation fdb3632_f085 rev. c1 test circuits and waveforms figure 15. unclamped energy test circ uit figure 16. unclamped energy waveforms figure 17. gate charge test circ uit figure 18. gate charge waveforms figure 19. switching time test circ uit figure 20. switching time waveforms t p v gs 0.01 ? l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0 v gs + - v ds v dd dut i g(ref) l v dd q g(th) v gs = 2v q g(tot) v gs = 10v v ds v gs i g(ref) 0 0 q gs q gd q gs2 v gs r l r gs dut + - v dd v ds v gs t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0
fdb3632_f085 ?2012 fairchild semiconductor corporation fdb3632_f085 rev. c1 thermal resistance vs. mounting pad area the maximum rated junction temperature, t jm , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, p dm , in an application. therefore the application?s ambient temperature, t a ( o c), and thermal resistance r ja ( o c/w) must be reviewed to ensure that t jm is never exceeded. equation 1 mathematically represents the relationship and serves as the basis for establ ishing the rating of the part. in using surface mount dev ices such as the to-263 package, the environment in which it is applied will have a significant influence on the part?s current and maximum power dissipation ratings. precise determination of p dm is complex and influenced by many factors: 1. mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. the number of copper layers and the thickness of the board. 3. the use of external heat sinks. 4. the use of thermal vias. 5. air flow and board orientation. 6. for non steady state applications, the pulse width, the duty cycle and the transient t hermal response of the part, the board and the environment they are in. fairchild provides thermal information to assist the designer?s preliminary appli cation evaluation. figure 21 defines the r ja for the device as a function of the top copper (component side) area. this is for a horizontally positioned fr-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. this graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. pulse applications can be evaluated using the fairchild device spice thermal model or manual ly utilizing the normalized maximum transient thermal impedance curve. thermal resistances corres ponding to other copper areas can be obtained from figure 21 or by calculation using equation 2 or 3. equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeters square. the area, in square in ches or square centimeters is the top copper area including the gate and source pads. (eq. 1 ) p dm t jm t a ? () r ja ----------------------------- = area in inches square d (eq. 2 ) r ja 26.51 19.84 0.262 area + () ------------------------------------ - + = (eq. 3 ) r ja 26.51 128 1.69 area + () --------------------------------- - + = area in centimeters square d figure 21. thermal r esistance vs mounting pad area 20 40 60 80 11 0 0.1 r ja = 26.51+ 19.84/(0.262+area) eq.2 r ja ( o c/w) area, top copper area in 2 (cm 2 ) (0.645) (6.45) (64.5 ) r ja = 26.51+ 128/(1.69+area) eq.3
fdb3632_f085 ?2012 fairchild semiconductor corporation fdb3632_f085 rev. c1 pspice electri cal model .subckt fdb3632 2 1 3 ; rev may 2002 ca 12 8 1.7e-9 cb 15 14 2.5e-9 cin 6 8 6.0e-9 dbody 7 5 dbodymod dbreak 5 11 dbreakmod dplcap 10 5 dplcapmod ebreak 11 7 17 18 102.5 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 6 10 6 8 1 evthres 6 21 19 8 1 evtemp 20 6 18 22 1 it 8 17 1 lgate 1 9 5.61e-9 ldrain 2 5 1.0e-9 lsource 3 7 2.7e-9 rlgate 1 9 56.1 rldrain 2 5 10 rlsource 3 7 27 mmed 16 6 8 8 mmedmod mstro 16 6 8 8 mstromod mweak 16 21 8 8 mweakmod rbreak 17 18 rbreakmod 1 rdrain 50 16 rd rainmod 3.8e-3 rgate 9 20 1.1 rslc1 5 51 rslcmod 1.0e-6 rslc2 5 50 1.0e3 rsource 8 7 rsourcemod 2.5e-3 rvthres 22 8 rvthresmod 1 rvtemp 18 19 rvtempmod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 22 19 dc 1 eslc 51 50 value={(v(5,51)/abs(v(5, 51)))*(pwr(v(5,51) /(1e-6*350),3))} .model dbodymod d (is=5.9e-11 n=1.07 rs=2.3e-3 trs1=3.0e-3 trs2=1.0e-6 + cjo=4e-9 m=0.58 tt=4.8e-8 xti=4.2) .model dbreakmod d (rs=0.17 trs1=3.0e-3 trs2=-8.9e-6) .model dplcapmod d (cjo=15e-10 is=1.0e-30 n=10 m=0.6) .model mstromod nmos (vto=4.1 kp=20 0 is=1e-30 n=10 tox=1 l=1u w=1u) .model mmedmod nmos (vto=3.4 kp=10.0 is =1e-30 n=10 tox=1 l=1u w=1u rg=1.1) .model mweakmod nmos (vto=2.75 kp=0.05 is=1e-30 n=10 tox=1 l=1u w=1u rg=1.1e+1 rs=0.1) .model rbreakmod res (tc1=1.0e-3 tc2=-1.7e-6) .model rdrainmod res (t c1=8.5e-3 tc2=2.8e-5) .model rslcmod res (tc1=2.0e-3 tc2=2.0e-6) .model rsourcemod res (tc1=4e-3 tc2=1e-6) .model rvthresmod res (tc1=-4.0e-3 tc2=-1.8e-5) .model rvtempmod res (t c1=-4.4e-3 tc2=2.2e-6) .model s1amod vswitch (ron=1e-5 roff=0.1 von=-4 voff=-2) .model s1bmod vswitch (ron=1e-5 roff=0.1 von=-2 voff=-4) .model s2amod vswitch (ron=1e- 5 roff=0.1 von=-0.8 voff=0.4) .model s2bmod vswitch (ron=1e- 5 roff=0.1 von=0.4 voff=-0.8) .ends note: for further discussion of the pspice model, consult a new pspice sub-circuit for the power mosfet featuring global temperature options ; ieee power electronics specialist conference records, 1991, written by william j. hepp and c. frank wheatley. 18 22 + - 6 8 + - 5 51 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource sourc e 11 7 3 lsource rl source cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap eslc rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6
fdb3632_f085 ?2012 fairchild semiconductor corporation fdb3632_f085 rev. c1 saber electrical model rev may 2002 template fdb3632 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=5.9e-11,nl= 1.07,rs=2.3e-3,trs1=3.0e-3,trs2=1.0e- 6,cjo=4e-9,m=0.58,tt=4.8e-8,xti=4.2) dp..model dbreakmod = (rs=0. 17,trs1=3.0e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=15e- 10,isl=10.0e-30,nl=10,m=0.6) m..model mstrongmod = (type=_n,v to=4.1,kp=200,is= 1e-30, tox=1) m..model mmedmod = (type=_n,vto =3.4,kp=10.0,is =1e-30, tox=1) m..model mweakmod = (typ e=_n,vto=2.75,kp= 0.05,is=1e-30, tox=1,rs=0.1) sw_vcsp..model s1amod = (ron=1e -5,roff=0.1,vo n=-4,voff=-2) sw_vcsp..model s1bmod = (ron=1e -5,roff=0.1,vo n=-2,voff=-4) sw_vcsp..model s2amod = (ron=1e -5,roff=0.1,von= -0.8,voff=0.4) sw_vcsp..model s2bmod = (ron=1e -5,roff=0.1,von= 0.4,voff=-0.8) c.ca n12 n8 = 1.7e-9 c.cb n15 n14 = 2.5e-9 c.cin n6 n8 = 6.0e-9 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod spe.ebreak n11 n7 n17 n18 = 102.5 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 i.it n8 n17 = 1 l.lgate n1 n9 = 5.61e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 2.7e-9 res.rlgate n1 n9 = 56.1 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 27 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=1.0e-3,tc2=-1.7e-6 res.rdrain n50 n16 = 3.8e-3, tc1=8.5e-3,tc2=2.8e-5 res.rgate n9 n20 = 1.1 res.rslc1 n5 n51 = 1.0e -6, tc1=2.0e-3,tc2=2.0e-6 res.rslc2 n5 n50 = 1.0e3 res.rsource n8 n7 = 2.5e-3, tc1=4e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-4.0e-3,tc2=-1.8e-5 res.rvtemp n18 n19 = 1, tc1=-4.4e-3,tc2=2.2e-6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v( n5,n51))))*((abs(v(n5,n51)*1e6/350))** 3)) } } 18 22 + - 6 8 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource sourc e 11 7 3 lsource rlsource cin r drain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplc ap iscl rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6
fdb3632_f085 ?2012 fairchild semiconductor corporation fdb3632_f085 rev. c1 spice thermal model rev may 2002 fdb3632 ctherm1 th 6 7.5e-3 ctherm2 6 5 8.0e-3 ctherm3 5 4 9.0e-3 ctherm4 4 3 2.4e-2 ctherm5 3 2 3.4e-2 ctherm6 2 tl 6.5e-2 rtherm1 th 6 3.1e-4 rtherm2 6 5 2.5e-3 rtherm3 5 4 2.2e-2 rtherm4 4 3 8.1e-2 rtherm5 3 2 1.35e-1 rtherm6 2 tl 1.5e-1 saber thermal model saber thermal model fdb3632 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =7.5e-3 ctherm.ctherm2 6 5 =8.0e-3 ctherm.ctherm3 5 4 =9.0e-3 ctherm.ctherm4 4 3 =2.4e-2 ctherm.ctherm5 3 2 =3.4e-2 ctherm.ctherm6 2 tl =6.5e-2 rtherm.rtherm1 th 6 =3.1e-4 rtherm.rtherm2 6 5 =2.5e-3 rtherm.rtherm3 5 4 =2.2e-2 rtherm.rtherm4 4 3 =8.1e-2 rtherm.rtherm5 3 2 =1.35e-1 rtherm.rtherm6 2 tl =1.5e-1 } rtherm4 rtherm6 rtherm5 rtherm3 rtherm2 rtherm1 ctherm4 ctherm6 ctherm5 ctherm3 ctherm2 ctherm1 tl 2 3 4 5 6 th junction case
trademarks the following includes registered and unregistered trademarks and service marks, owned by fairch ild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes with out further notice to any products herein to improve reliability, function, or design. fairchild does not assume an y liability arising out of th e application or use of any product or circuit described herein; neither does it convey an y license under its patent rights, nor the rights of others. these specifications do not expand the term s of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized fo r use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used here in: 1. life support devices or systems ar e devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms 2cool? 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truecurrent ? * serdes? uhc ? ultra frfet? unifet? vcx? visualmax? voltageplus? xs? tm ? ? tm datasheet identification product status definition advance information formative / in design datasheet contains the design specifications for product development. specifications may change in any manner without notice. preliminary first production datasheet contains preliminary data; supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice to improve design. no identification needed full production datasheet contains final specifications. fa irchild semiconductor reserves the right to make changes at any time without notice to improve the design. obsolete not in production datasheet contains specifications on a product t hat is discontinued by fairchild semiconductor. the datasheet is for reference information only. anti-counterfeiting policy fairchild semiconductor corporation?s anti-counterfeiting policy . fairchild?s anti-counterfeiting policy is also stated on our external website, www.fairchildsemi.com, under sales support . counterfeiting of semiconductor parts is a growing problem in th e industry. all manufactures of semiconductor products are expe riencing counterfeiting of their parts. customers who inadvertently purchase counterfeit parts experience many problems su ch as loss of brand reputation, substa ndard performance, failed application, and increased cost of production and manufacturing de lays. fairchild is taking strong measures to protect ourselve s and our customers from the proliferation of counterfeit parts. fairchild strongly encourages customers to purchase fairchild parts either directly from fairchild or from authorized fairchild distributors who are listed by country on our web page cited above . products customers buy either from fairchild directly or fr om authorized fairchild distributors are genuine parts, have full traceability, meet fa irchild?s quality standards for handing and storage and provide access to fairchild?s full range of up-to-date technical and product information. fairchild and our authorized distributors will stand behind all warranties and wi ll appropriately address and warranty issues that may arise. fairchild will not provide any warranty coverage or other assistance for parts bought from unau thorized sources. fairchild is committed to combat this global problem and encourage our customer s to do their part in stopping th is practice by buying direct or from authorized distributors. rev. i60 tm ? ?2012 fairchild semiconductor corporation fdb3632_f085 rev. c1

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